Casio SF-5600AR Specifications download pdf (Page 15)

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VIN

VSS

KAC

KIO

ADDRESS BUS

2 MHz

VDD1

MAIN SWITCH

GND

VDD

(Pin53)

(Pin54)

(Pin41)

VDD

"H"

ADDRESS

DATA

VDD

"L"

OSCO

OSCI

(Pin70)

INT0

V2ON

Gate array

DATA BUS

(Pin40)

(Pin45)

(Pin36)

"L"

(Pin24)

9-1. System chart

Generally, SF-5600AR is working with the following steps.

1. Supply 5V to VDD1 and VDD2.

2. Output "L" from SWO terminal.

3. Output "L" from IC4 and Q5 terminal.

4. Main switch ON.

5. Input "L" to SW terminal.

6. Input "L" from KAC terminal.

7. Push power on button switch.

8. CPU oscillation is generated.

9. Output "H" from V2ON terminal.

10. Output "L" from VOB terminal.

OFF

9. CIRCUIT EXPLANATIONS

CPU

HD62076C03

PDN

"L"

SWO

"L"

µPD23C2001EGW-344

(Operation program)

ROM

VOB

(Pin3)

(Pin1)

"H"

"L"

(Pin2)

OEO

(Pin62)

(Pin35)

"L"

(Pin58)

(Pin28)

MSO

(Pin49)

"L"

(Pin24)

(Pin22)

Transistor Q3

Power supply

circuit

V1~V5

for LCD

IC4

VDD

Low battery

detector

11. Apply VDD to ROM.

12. Output all LCD drive voltages.

13. Gate array sends ROM output enable

signal to OE terminal.

14. Gate array sends ROM Chip enable

signal to CE terminal.

15. CPU sends address to ROM.

16. CPU receives data from ROM.

VDD

SSC2571F0A

VCC

GND

1 ... 14 15 16 ... 33

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Casio SF-5600AR Specifications Page 15

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